In a level shift circuit having a low voltage power supply and a high voltage power supply as exemplified in JP 2007-201704 A, for example, an operating current to a differential pair is cut off in accordance with an input signal state to reduce current consumption. In this configuration, when signals of an input terminal and an output terminal are at high levels, for example, these signals are subjected to a logic operation by a NAND circuit to cut off the operating current of the differential pair in response to an output of the NAND circuit.
When the two power supplies are activated, a low voltage power supply voltage occasionally rises later than a high voltage power supply voltage. When the low voltage power supply voltage rises with delay under a state of no input signal and high impedance, outputs of the NAND circuit and inverter circuit, which are operated with the low voltage power supply, often become unstable. A cut-off transistor forming a differential pair and a transistor at an output stage responsively turns on. As a result, the output signal is not maintained at a high level and changed to a low level.